PCIe DEVICE AND OPERATING METHOD THEREOF

ABSTRACT

A peripheral component interconnect express (PCIe) device includes a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host. Each function type may be a physical function type, a virtual function type, or a disable function type.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2021-0048063, filed on Apr. 13, 2021, which is incorporated herein by reference in its entirety.

BACKGROUND Field of Invention

The present disclosure relates to an electronic device, and more particularly, to a Peripheral Component Interconnect Express (PCIe) device and an operating method thereof.

Description of Related Art

A Peripheral Component Interconnect Express (PCIe) device may define a bus protocol which is used to connect input/output devices to a host device. PCI Express (PCIe) has the concept of programming defined by the PCI standards and includes a physical communication layer defined as a high-speed serial interface.

A storage device may store data in response to control of a host device such as a computer or a smartphone. The storage device may include a memory device which stores data and a memory controller which controls the memory device. Memory devices may be divided into volatile memory devices and non-volatile memory devices.

A volatile memory device may retain data as long as power is being supplied, and may lose the stored data in the absence of power supply. Types of volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

A non-volatile memory device may not lose data even in the absence of power supply. Types of non-volatile memory devices may include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM) and flash memory.

SUMMARY

Various embodiments are directed to a Peripheral Component Interconnect Express (PCIe) device reducing power consumption and a device size by decreasing a PCIe gate count, and an operating method thereof.

In addition, various embodiments of the present disclosure are directed to a PCIe device efficiently arranging functions configured in various types by using a software method such as a request from a host and firmware setting, not by hardware modifications, and an operating method thereof.

According to an embodiment, a peripheral component interconnect express (PCIe) device may include a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host.

According to an embodiment, a method for operating a Peripheral Component Interconnect Express (PCIe) device including a plurality of common functions performing operations associated with a PCIe interface, the method may include receiving function type setting information from the host, determining a plurality of function types for the plurality of common functions, respectively, based on the function type setting information, each function type being one of a physical function (PF) type, a virtual function (VF) type, and a disable function type in which the operations are disabled, and controlling the plurality of common functions according to the plurality of function types, respectively, to perform the operations.

According to an embodiment, a peripheral component interconnect express (PCIe) device may include a first function performing operations associated with a Peripheral Component Interconnect Express (PCIe) interface according to a physical function (PF) type, a second function performing operations associated with the PCIe interface according to the physical function type or a virtual function (VF) type, and a function type controller changing a function type of the second function into the virtual function type or the physical function type based on function type setting information provided from a host.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a computing system according to an embodiment of the present disclosure;

FIG. 2 illustrates another example of a computing system according to an embodiment of the present disclosure;

FIG. 3 illustrates another example of a computing system according to an embodiment of the present disclosure;

FIG. 4 illustrates a multi-function device according to an embodiment of the present disclosure;

FIG. 5 illustrates an example of a PCIe device that is single root input/output virtualization (SR-IOV) capable according to an embodiment of the present disclosure;

FIG. 6 illustrates another example of a PCIe device using SR-IOV according to an embodiment of the present disclosure;

FIG. 7 illustrates a PCIe device according to an embodiment of the present disclosure;

FIG. 8 illustrates a common function according to an embodiment of the present disclosure;

FIG. 9 illustrates a configuration space layout according to an embodiment of the present disclosure;

FIG. 10 illustrates an example of a PCIe device according to an embodiment of the present disclosure;

FIG. 11 illustrates another example of a PCIe device according to an embodiment of the present disclosure;

FIG. 12 illustrates another example of a PCIe device according to an embodiment of the present disclosure;

FIG. 13 illustrates another example of a PCIe device according to an embodiment of the present disclosure;

FIG. 14 illustrates another example of a PCIe device according to an embodiment of the present disclosure;

FIG. 15 illustrates another example of a PCIe device according to an embodiment of the present disclosure;

FIG. 16A illustrates an example of a reset operation according to an embodiment of the present disclosure;

FIG. 16B illustrates another example of a reset operation according to an embodiment of the present disclosure;

FIG. 16C illustrates another example of a reset operation according to an embodiment of the present disclosure;

FIG. 16D illustrates another example of a reset operation according to an embodiment of the present disclosure; and

FIG. 17 is a flowchart illustrating an operating process of PCIe according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Specific structural or functional descriptions of examples of embodiments in accordance with concepts which are disclosed in this specification are illustrated only to describe the examples of embodiments in accordance with the concepts and the examples of embodiments in accordance with the concepts may be carried out by various forms but the descriptions are not limited to the examples of embodiments described in this specification.

FIG. 1 illustrates an example of a computing system 100 according to an embodiment of the present disclosure.

Referring to FIG. 1, the computing system 100 may include a host 1000 and a Peripheral Component Interconnect Express (PCIe) device 2000. The computing system 100 may be, for example, a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC, or an in-vehicle infotainment system.

The host 1000 may include a processor 1100, a memory 1200, an input/output (I/O) manager 1300, and a bus 1400. Components of the host 1000 may exchange signals and data through the bus 1400.

The processor 1100 may include circuits, interfaces, or program codes for processing data and controlling operations of components of the computing system 100. For example, the processor 1100 may include a CPU (such as an ARM™ processor), a microcontroller, or an application specific integrated circuit (ASIC).

The memory 1200 may include SRAM or DRAM that stores data, commands, or program codes necessary for operations of the computing system 100. However, the processor 1100 may also include a non-volatile memory. According to an embodiment, the memory 1200 may include program codes that may operate to execute one or more operating systems (OS) and virtual machines (VM) and program codes that execute a virtualization intermediary (VI) for managing the virtual machines.

The processor 1100 may execute one or more operating systems and virtual machines by driving the program codes stored in the memory 1200. In addition, the processor 1100 may execute the virtualization intermediary for managing the virtual machines. In this manner, the processor 1100 may control operations of the components of the computing system 100.

The I/O manager 1300 may be an adapter that connects input/output devices to the host 1000. For example, the I/O manager 1300 may include a Universal Serial Bus (USB) adapter, a Peripheral Component Interconnect (PCI) or a PCI Express (PCIe) adapter, a Small Computer System Interface (SCSI) adapter, a Serial AT Attachment (SATA) adapter, a NonVolatile Memory express (NVMe) adapter, or combinations thereof. The I/O manager 1300 may include circuits, interfaces, or codes that are operable to communicate information with devices connected to the computing system 100. The I/O manager 1300 may include one or more standardized buses and one or more bus controllers. Therefore, the I/O manager 1300 may perceive the devices connected to the bus 1400, list the devices connected to the bus 1400, and perform resource allocation and deallocation for various devices connected to the bus 1400. In other words, the I/O manager 1300 may operate to manage communications over the bus 1400. For example, the I/O manager 1300 may be a PCI or PCIe system and include PCIe root complex (RC), one or more PCIe switches, or bridges. For example, the I/O manager 1300 may be controlled by the virtualization intermediary.

PCI may define a bus protocol that is used to connect the I/O devices to the processor 1100. PCIe may have the concept of programming defined by the PCI standards and define a physical communication layer as a high-speed serial interface.

The PCIe device 2000 may communicate with the host 1000 using PCIe. For example, the PCIe device 2000 may be implemented as various I/O device types such as networks and storages.

According to an embodiment, the PCIe device 2000 may be defined as an endpoint or a device including an endpoint.

An endpoint may refer to a type of a function that may be a requester or a completer of a PCIe transaction. Endpoints may be classified into legacy endpoints, PCI Express (PCIe) endpoints, or root complex integrated (RCiEP) endpoints.

A legacy endpoint may be a function with a type 00h configuration header. A legacy endpoint may support configuration requests as a completer. A legacy endpoint may support I/O requests as a completer. A legacy endpoint may accept I/O requests for either or both of 80h and 84h locations regardless of an I/O decode configuration of the corresponding endpoint. A legacy endpoint may support I/O requests. A legacy endpoint must not issue a locked request. A legacy endpoint may implement extended configuration space capabilities. A legacy endpoint operating as a requester of a memory transaction may not be required to generate addresses of 4 GB or more. When an interrupt resource is requested, a legacy endpoint may be required to support Message Signaled Interrupt (MSI) or MSI-X, or both. When MSI is implemented, a legacy endpoint may support a 32-bit or 64-bit message address version with an MSI functional structure. A legacy endpoint may support 32-bit address designation with respect to a base address register requesting a memory resource. A legacy endpoint may appear within one of the hierarchy domains originated by a root complex.

A PCIe endpoint may be a function with a type 00h configuration space header. A PCIe endpoint may support configuration requests as a completer. A PCIe endpoint must not depend on operating system allocation of I/O resources claimed through base address registers (BARs). A PCIe endpoint may not generate I/O requests. A PCIe endpoint may not support locked requests as a completer or generate locked requests as a requester. PCIe-compliant software drivers and application programs may be written to prevent the use of lock semantics when accessing a PCIe endpoint. A PCIe endpoint operating as a requester of a memory transaction may generate an address of more than 4 GB. A PCIe endpoint may be required to support Message Signaled Interrupt (MSI), MSI-X, or both when an interrupt resource is requested. When MSI is implemented, a PCIe endpoint may support a 64-bit message address version with an MSI functional structure. A minimum address range requested by a base address register may be 128 bytes. A PCIe endpoint may appear within one of the hierarchy domains originated by a root complex.

RCiEPs may be implemented on internal logic of root complexes that contains root ports. An RCiEP may be a function with a type 00h configuration space header. An RCiEP may support configuration requests as a completer. An RCiEP may not request I/O resources claimed through base address registers. An RCiEP may not generate I/O requests. An RCiEP may not support locked requests as a completer or generate locked requests as a requester. PCIe-compliant software drivers and application programs may be written to prevent the use of lock semantics when accessing an RCiEP. An RCiEP operating as a requester of a memory transaction may generate an address equal to or greater than that which may be processed by the host 1000 as a completer. An RCiEP may be required to support MSI, MSI-X, or both when an interrupt resource is requested. When MSI is implemented, an RCiEP may support a 32-bit or 64-bit message address version with an MSI functional structure. An RCiEP may support 32-bit address designation with respect to a base address register requesting a memory resource. An RCiEP may implement link capabilities, link status, link control, link capabilities 2, link status 2, and link control 2 registers in the PCIe extended capability. An RCiEP may not implement active state power management. An RCiEP may not be hot-plugged independent of the root complex as a whole. An RCiEP may not appear in hierarchy domains exposed by the root complex. An RCiEP may not appear in switches.

According to an embodiment, the PCIe device 2000 may generate at least one virtual device. For example, the PCIe device 2000 may store program codes for generating at least on virtual device.

According to an embodiment, the PCIe device 2000 may generate a physical function (PF) device or a virtual function (VF) device in response to a virtualization request received from the host 1000. For example, a physical function device may be set to a virtual device in which a virtualization intermediary is granted access rights. A virtual function device may be set to a virtual device that is assigned to a virtual machine of the host 1000.

FIG. 2 illustrates another example (a computing system 200) of a computing system according to an embodiment of the present disclosure.

According to an embodiment, FIG. 2 shows an example of a general platform configuration where PCIe is available.

Referring to FIG. 2, the computing system 200 may include the processor 1100, the memory 1200, a plurality of system images 210-1 to 210-n, a virtualization intermediary 220, a root complex 230, a switch 240, and a plurality of PCIe devices 2000-1 to 2000-3.

The processor 1100 and the memory 1200 as shown in FIG. 2 may correspond to the processor 1100 and the memory 1200 as shown in FIG. 1, respectively. According to an embodiment, the processor 1100, the memory 1200, the plurality of system images 210-1 to 210-n, the virtualization intermediary 220, the root complex 230, and the switch 240 may be included in the host 1000 of FIG. 1. According to an embodiment, the plurality of PCIe devices 2000-1 to 2000-3 may correspond to the PCIe device 2000 of FIG. 1.

The system images 210-1 to 210-n may refer to software components that are executed in a virtual system to which PCIe functions are assigned. The system images 210-1 to 210-n may be software such as operating systems that are used to execute applications or reliable services. For example, each of the system images 210-1 to 210-n may be respectively configured as a guest OS, a shared or non-shared I/O device driver, or the like. To increase effective hardware resource utilization without hardware modifications, the plurality of system images 210-1 to 210-n may be executed in the computing system 200.

According to an embodiment, a PCIe function may refer to an independent operation unit for providing physical resources included in the PCIe devices 2000-1 to 2000-3. In the present disclosure, a PCIe function and a “function” may refer to the same meaning.

The virtualization intermediary 220 may be a software component that supports one or more system images 210-1 to 210-n. According to an embodiment, the virtualization intermediary 220 may be referred to as hypervisor or a virtual machine monitor (VMM). The virtualization intermediary 220 may be interposed between hardware such as the processor 1100 and the memory 1200 and the system images 210-1 to 210-n. I/O operations (inbound or outbound) in the computing system 200 may be intercepted and processed by the virtualization intermediary 220. The virtualization intermediary 220 may present abstract the hardware resources to present the system images 210-1 to 210-n with its own virtual system. The actual hardware resources available to each of the system images 210-1 to 210-n may vary depending on workload or customer-specific policies.

The root complex 230 may signify the root of an I/O hierarchy that connects the processor 1100/memory 1200 subsystem to an I/O. According to an embodiment, the root complex 230 may be implemented as one configuration of the I/O manager 1300 as shown in FIG. 1.

The computing system 200 may include at least one root complex 230. In addition, each root complex 230 may include one or more root ports 231-1 and 232-2. Each of the root ports 231-1 and 232-2 may show a separate hierarchy. The root complex 230 may communicate with the switch 240 or the PCIe devices 2000-1 to 2000-3 through the root ports 231-1 and 232-2.

The capability to route peer-to-peer transactions between hierarchy domains through the root complex 230 may be optional. A hierarchy domain may be composed of a single endpoint or a sub-hierarchy containing one or switches and endpoints.

The root complex 230 may split a packet into smaller packets when routing peer-to-peer transactions between hierarchy domains. For example, the root complex 230 may a single packet having a 256-byte payload into two packets each having a 128-byte payload. However, the root complex 230 that supports peer-to-peer routing of vendor-defined messages may not split a vendor-defined message into smaller packets except at 128-byte boundaries (i.e., all resulting packets except the last packet must be an integral multiple of 128 bytes).

The root complex 230 may support generation of configuration requests as a requester. The root complex 230 may support the generation of I/O requests as a requester.

The root complex 230 may not support lock semantics as a completer. The root complex 230 may support generation of locked requests as a requester.

The switch 240 may be defined as a logical assembly of various virtual PCI-to-PCI bridges. The switch 240 may communicate with the PCIe devices 2000-2 and 2000-3.

The switch 240 may appear as configuration software with two or more logical PCI-to-PCI bridges.

The switch 240 may forward transactions using PCI bridge mechanisms. The switch 240 may forward all types of transaction layer packets (TLPs) between all port sets. The switch 240 may support locked requests.

The switch 240 may not be allowed to split a packet into smaller packets.

Arbitration between ingress ports of the switch 240 may be implemented using round robin or weighted round robin when contention occurs on the same virtual channel.

Endpoints may not appear in configuration software on the internal bus of the switch 240 as peers of the virtual PCI-to-PCI bridges representing the switch downstream ports.

FIG. 3 illustrates another example (a computing system 300) of a computing system according to an embodiment of the present disclosure.

According to an embodiment, FIG. 3 shows an example of a Single Root input/output Virtualization (SR-IOV) configuration platform.

Single Root I/O Virtualization (SR-IOV) may enable the system images 210-1 to 210-n to share PCIe hardware resources in a virtual environment. According to an embodiment, SR-IOV may be developed to improve I/O performance of the PCIe devices 2000-1 to 2000-3 and directly connect the system images 210-1 to 210-n and the PCIe devices 2000-1 to 2000-3. Therefore, in the computing system 300 that contains SR-IOV capability, one or more PCIe devices 2000-1 to 2000-3 or PCIe functions may be assigned to one of the system images 210-1 to 210-n. According to an embodiment, the SR-IOV capability may have a specification that a single PCIe device (2000-1 to 2000-3) may appear as individual PCI devices 2000-1 to 2000-3 on the system image (210-1 to 210-n) under a single root port. According to an embodiment, the PCIe devices 2000-1 to 2000-3 supporting the SR-IOV capability may display a plurality of instances, i.e., PCIe functions on the system images 210-1 to 210-n. In addition, in the computing system 300 to which the SR-IOV capability is applied, the root complex 230 may directly connect the system images 210-1 to 210-n to the PCIe functions without the virtualization intermediary 220. Therefore, by using the SR-IOV capability, the root complex 230 may directly connect the system images 210-1 to 210-n of the host 1000 to the PCIe functions not via the virtualization intermediary 220.

Referring to FIG. 3, the computing system 300 may include the processor 1100, the memory 1200, the plurality of system images 210-1 to 210-n, the virtualization intermediary 220, the root complex 230, the switch 240, a single root PCI manager (SR-PCIM) 310, a translation agent (TA) 320, an address translation and protection table (ATPT) 330, and the plurality of PCIe devices 2000-1 to 2000-3.

Relative to the computing system 200 of FIG. 2, the computing system 300 as shown in FIG. 3 may further include the single root PCI manager 310, the translation agent 320, and the address translation and protection table 330.

The plurality of PCI devices 2000-1 to 2000-3 as shown in FIG. 3 may correspond to the plurality of PCIe devices 2000-1 to 2000-3 of FIG. 2. In addition, each of the PCIe devices 2000-1 to 2000-3 may include an address translation cache (ATC) 341, a physical function (PF) 342, and a plurality of virtual functions (VF) 343. For convenience of explanation, FIG. 3 illustrates one physical function. However, according to embodiments, there may be a plurality of physical functions.

The single root PCI manager 310 may include software responsible for the configuration of the SR-IOV capability, management of the physical functions 342 and the virtual functions 343, processing of associated error events, and overall device controls such as power management and hot plug services. According to an embodiment, the single root PCI manager 310 may be logically located in the virtualization intermediary 220.

The translation agent 320 may be hardware, or a combination of hardware and software responsible for translating an address within a PCIe transaction into an associated platform physical address. The translation agent 320 may include an address translation cache to accelerate translation table access. In addition, the translation agent 320 may support address translation services (ATS) which enables a PCIe function to obtain address translations a priori to DMA access to the associated memory. In an SR-IOV implementation, the use of the translation agent 320 may be optional.

The address translation and protection table 330 may contain the set of address translations accessed by the translation agent 320 to process PCIe requests (DMA read, DMA write, or interrupt request). In PCIe, interrupts may be treated as memory write operations. Through a combination of a requester identifier and an address contained within a PCIe transaction, an interrupt may be routed to any target (e.g., a processor core) transparent to the associated I/O function. DMA read and write requests may be translated through a combination of a routing ID and the address contained within the PCIe transaction. The use of the address translation and protection table 330 may be optional in an SR-IOV implementation.

The address translation cache 341 may exist in two locations within a platform. For example, the address translation cache 341 may be integrated within the translation agent 320, located in an RC, or located in the PCIe devices 2000-1 to 2000-3. In the PCIe devices 2000-1 to 2000-3, the address translation cache 341 may be populated using the ATS technology. A PCIe transaction indicating that a translated address is contained may bypass the address translation cache 341 of a platform to improve performance without damaging advantages related to the address translation and protection table 330. The use of the address translation cache 341 may be optional in an SR-IOV implementation.

The physical function 342 may be a PCIe function that supports the SR-IOV capability and accesses the single root PCI manager 310, the virtualization intermediary 220 or the system images 210-1 to 210-n.

The virtual function 343 may be a light-weight PCIe function that may directly access the system images 210-1 to 210-n. The virtual function 343 may operate as a virtual instance of the physical function 342. Thus, from point-of-view of the system images 210-1 to 210-n, the virtual function 343 may appear as an instance of the physical function 342. Resources associated with a main data movement of a function may be used in the system images 210-1 to 210-n. The virtual function 343 may be shared serially by different system images 210-1 to 210-n. For example, the virtual function 343 may be assigned to one system image (210-1 to 210-n), reset, and then be assigned to another system image (210-1 to 210-n). The virtual function 343 may be selectively migrated from one physical function 342 to another function. All virtual functions 343 associated with the physical function 342 may be the same device type as the physical function 342 (e.g., the same network device type or the same storage device type).

FIG. 4 illustrates a multi-function device according to an embodiment of the present disclosure.

A PCIe device 400 as shown in FIG. 4 may represent one of the PCIe device 2000 as shown in FIG. 1 and the PCIe devices 2000-1 to 2000-3 as shown in FIGS. 2 and 3.

Referring to FIG. 4, the PCIe device 400 may include a plurality of functions Function 0 to Function N. According to an embodiment, the plurality of functions Function 0 to Function N may be physical functions. When all functions Function 0 to Function N included in the PCIe device 400 are physical functions, the corresponding PCIe device 400 may be defined as a multi-function device.

According to an embodiment, the plurality of functions Function 0 to Function N may share a common PCIe link. The link and PCIe functionality shared by all functions Function 0 to Function N may be managed through the zeroth function Function 0.

According to an embodiment, the plurality of functions Function 0 to Function N may support the Alternative Routing Identifier (ARI) capability. In addition, the plurality of Alternative Routing Identifier (ARI) capability may use a single bus number captured through a PCI enumeration process.

According to an embodiment, the plurality of functions Function 0 to Function N may support ATS capability. The plurality of functions Function 0 to Function N may include an address translation cache for managing an ATS obtained translated address.

According to an embodiment, each of the plurality of functions Function 0 to Function N may include unique physical resources including a separate configuration space, a base address register (BAR), and the like. The physical resources may refer to some of the physical resources of the PCIe device 400. In other words, the plurality of functions Function 0 to Function N may provide physical resources to the assigned system images.

The plurality of functions Function 0 to Function N may be assigned to the system images, respectively. To prevent one system image from impacting another system image, all PCIe configuration operations may be intercepted and processed by the virtualization intermediary.

According to an embodiment, the configuration space of each of the plurality of functions Function 0 to Function N may include a type 0 configuration space header. For example, the type 0 configuration space header may include a header type register and an interrupt pin register.

The header type register may be included in the type 0 configuration space header of the configuration space. The header type register may identify whether multi-functions may be included in a layout of a predefined second portion (starting from a 10h byte of the configuration space) and the PCIe device 400. For example, a multi-function device field of a header type register may be included. When the multi-function device field is set, the PCIe device 400 may include the plurality of functions Function 0 to Function N. Software may probe for the other functions Function 1 to Function N except for the zeroth function Function 0.

The interrupt pin register may be a read-only register that identifies a legacy interrupt message the function uses. Valid values may be 01h, 02h, 03h and 04h that are mapped to the legacy interrupt message for INTA, INTB, INTC and INTD, respectively. The value 00h may indicate that the function does not use the legacy interrupt message. The values 05h to FFh may be reserved. The PCI Express may define one legacy interrupt message for a single function device and define up to four legacy interrupt messages for the multi-function device. For the single function device, only INTA may be used. All functions Function 0 to Function N of the multi-function device may use INTx messages. When a device implements a single legacy interrupt message, it should be INTA. When two legacy interrupt messages are implemented, it should be INTA and INTB. For a multi-function device, all functions Function 0 to Function N may use the same INTx, or each may have its own (up to a maximum of four), or any combination thereof.

According to an embodiment, the configuration space of all functions Function 0 to Function N may be included in a PCIe capability structure. For example, the PCIe capability structure may include a PCIe capability register, a device capabilities register, a device control register, a device status register, a link capabilities register, a link control register, a link status register, a slot capabilities register, a slot control register, a slot status register, a root control register, a root capabilities register, a root status register, a device capabilities 2 register, a device control 2 register, a device status 2 register, a link capabilities 2 register, a link control 2 register, a link status 2 register, a slot capabilities 2 register, a slot control 2 register, a slot status 2 register, a root controller 2 register, a root capabilities 2 register, a root status 2 register, and the like.

The PCIe capability register may identify a PCIe device function type and associated capabilities. According to an embodiment, the PCIe capability register may be a 16-bit register. The bits 3:0 of the PCIe capability register may a capability version field. The capability version field may have a read only attribute. More specifically, the capability version field may indicate a PCI-SIG defined PCI Express function structure version number. The bits 7:4 of the PCIe capability register may be a device/port type field. The device/port type field may have a read only attribute. More specifically, the device/port type field may indicate a specific type of a function. In the device/port type field, functions of a multi-function device may refer to different types. The bit 8 of the PCIe capability register may be a slot implemented field. The slot implemented field may have a hardware initialized (HwInit) attribute. When the slot implemented field is set, it may mean that a link connected to this port is connected to a slot. The bits 13:9 of the PCIe capability register may be an interrupt message number field. The interrupt message number field may have a read only attribute. The interrupt message number field may indicate which MSI/MSI-X vector is used for an interrupt message generated in association with a status bit with a function structure. For MSI, a value of the interrupt message number field may indicate an offset between a base message data and the generated interrupt message. For MSI-X, the value of the interrupt message number field may indicate an MSI-X table entry used to generate the interrupt message. When both MSI and MSI-X are implemented, MSI and MSI-X may be permitted to use different vectors though software must enable only one mechanism at a time. For example, when MSI-X is enabled, the value of the interrupt message number field may indicate an MSI-X vector. When MSI is enabled, or none of them is enabled, the value of the interrupt message number field may indicate a vector for MSI. When both MSI and MSI-X are enabled at the same time, the value in the interrupt message number field may not be defined. The bit 14 of the PCIe capability register may have a read only attribute and may not be defined.

The device capability register may identify PCIe device function-specific capabilities. According to an embodiment, the device capability register may be a 32-bit register. The bits 2:0 of the device capability register may be a maximum payload size supported (Max_Payload_Size Supported) field. The max payload size supported field may have a read only attribute. The max payload size supported field may indicate a maximum payload size that supports TLP. The functions Function 0 to Function N of the multi-function device may have different values for this field. The bits 4:3 of the device capability register may be a maximum payload size supported (Max_Payload_Size Supported) field. The phantom functions supported field may have a read only attribute. The phantom functions supported field may indicate the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining the unclaimed functions numbers with a tag identifier.

The device control register may control a PCIe device-specific parameter. According to an embodiment, the device control register may be a 16-bit register. The bit 0 of the device controller register may be a correctable error reporting enable field. The correctable error reporting enable field may control sending ERR_COR messages in conjunction with other bits. For the multi-function device, the correctable error reporting enable field may control error reporting of each function (Function 0 to Function N). The correctable error reporting enable field may have a read-write (RW) attribute. The bit 1 of the device controller register may be a non-fatal correctable error reporting enable field. The non-fatal correctable error reporting enable field may control sending ERR_NONFATAL messages in conjunction with other bits. For the multi-function device, the non-fatal error reporting enable field may control error reporting for each function (Function 0 to Function N) from point-of-view of each function (Function 0 to Function N). The non-fatal error reporting enable field may have a read-write attribute. The bit 2 of the device controller register may be a fatal error reporting enable field. The fatal correctable error reporting enable field may control sending ERR_FATAL messages in conjunction with other bits. For the multi-function device, the fatal error reporting enable field may control error reporting for each function (Function 0 to Function N) from a point-of-view of each function (Function 0 to Function N). The fatal error reporting enable field may have a read-write attribute. The bit 3 of the device controller register may be an unsupported request reporting enable field. The unsupported request reporting enable field may control signaling of unsupported request errors by sending error messages in conjunction with other bits. For the multi-function device, the unsupported request reporting enable field may control error reporting for each function (Function 0 to Function N) from point-of-view of each function (Function 0 to Function N). The unsupported request reporting enable field may have a read-write attribute. The bits 7:5 of the device control register may be a maximum payload size (Max_Payload_Size) field. The max payload size field may set the maximum TLP payload size for a function. As a receiver, a function must not generate TLPs exceeding a set value. As a transmitter, permissible values that may be indicated by the max payload size supported field of the function capability register. All functions Function 0 to Function N of the multi-function device may have different values in the max payload size field. For Alternative Routing Identifier (ARI) devices, the max payload size field may be determined solely by the setting in the zeroth function Function 0. The settings in the other functions may always return whatever values software programmed for each, but otherwise may be ignored by components. The max payload size field may have a read-write attribute.

The device status register may provide information about a PCIe device (function)-specific parameter. According to an embodiment, the device status register may be a 16-bit register. The bit 0 of the device status register may be a correctable error detected field. The correctable error detected field may indicate that correctable errors are detected. The correctable errors may be recorded in the error detected field regardless of whether error reporting is enabled in the device control register. For a multi-function device, each function (Function 0 to Function N) may indicate an error status that is perceived by each function (Function 0 to Function N). The correctable error detected field may have a Write-1-to-clear status (RW1C) attribute. The bit 1 of the device status register may be a non-fatal correctable error detected field. The non-fatal correctable error detected field may indicate that non-fatal errors are detected. The non-fatal errors may be recorded in the error detected field regardless of whether error reporting is enabled in the device control register. For a multi-function device, each function (Function 0 to Function N) may indicate an error status that is perceived by each function (Function 0 to Function N). A non-fatal error detected field may have an RW1C attribute. The bit 2 of the device status register may be a fatal error detected field. The fatal error detected field may indicate status of fatal errors detected. The fatal errors may be recorded in the fatal error detected field regardless of whether error reporting is enabled in the device control register. For a multi-function device, each function (Function 0 to Function N) may indicate an error status that is perceived by each function (Function 0 to Function N). A fatal error detected field may have an RW1C attribute. The bit 3 of the device status register may be an unsupported request field. The unsupported request detected field may indicate that a function has received unsupported requests. Errors may be recorded in the request detected field regardless of whether error reporting is enabled in the device control register. For a multi-function device, each function (Function 0 to Function N) may indicate an error status that is perceived by each function (Function 0 to Function N). The unsupported request detected field may have an RW1C attribute. The bit 6 of the device status register in an emergency power reduction detected field which may be set when the functions Function 0 to Function N enter emergency power reduction state. Each time a condition for which an emergency power reduction state is input exists, the functions Function 0 to Function N may maintain the emergency power reduction state. The multi-function device coupled to an upstream port may set the emergency power reduction detected field in all functions Function 0 to Function N that support the emergency power reduction state. The emergency power reduction detected field may have an RW1C attribute.

The link capability register may identify PCIe link-specific capability. For a multi-function device, field values of the link capability register of all functions Function 0 to Function N may be the same.

According to an embodiment, the configuration space of each of the plurality of functions Function 0 to Function N may include Message Signaled Interrupt (MSI) Capability Structures, Secondary PCI Express Extended Capability, Data Link Feature Extended Capability, and ACS Extended Capability. All functions Function 0 to Function N that generate interrupts may implement MSI or MSI-X.

In addition, the configuration space of each of the plurality of functions Function 0 to Function N may include various registers associated with the multi-function device in addition to the above-described registers.

According to an embodiment, the plurality of functions Function 0 to Function N may perform an error handling operation. For example, the plurality of functions Function 0 to Function N may perform an error handling operation using advanced error reporting (AER). For example, when an error is detected, the plurality of PCIe functions PCIe function 0 to PCIe function N may perform an error handling operation by indicating an error status through a completion status field, by sending an error message to a root complex, or by error forwarding.

According to an embodiment, the plurality of functions Function 0 to Function N may perform a function level reset (FLR) operation. For example, the plurality of functions Function 0 to Function N may perform a function level reset (FLR) operation at the request of a host.

A function level reset mechanism may enable software to quiesce and reset endpoint hardware with function-level granularity.

The function level reset may apply to each of the functions Function 0 to Function N. Only the target function (Function 0 to Function N) may be affected by a function level reset operation. The link status may not be affected by the function level reset.

The function level reset may modify the statuses of the functions Function 0 to Function N.

For example, except for sticky-type registers (ROS, RWS, RW1CS), HwInit type defined registers, and other such fields or registers, function registers and function-specific state machines may be set to initial values of function registers and function-specific state machines.

In addition, function level reset may modify function states such as a captured slot power limit value of a device capability register, a captured slot power limit scale of the device capability register, Max_Payload_Size of a device control register, Active State Power Management (ASPM) control of a link control register, a Read Completion Boundary (RCB) of the link control register, Common Clock Configuration of the link control register, Extended Synch of the link control register, Enable Clock Power Management of the link control register, Hardware Autonomous Width Disable of the link control register, Hardware Autonomous Speed Disable of a link control 2 register, a Link Equalization 8.0 GT/s request of a link state 2 register, a link equalization request 16.0 GT/s of a 16.0 GT/s state register, a Lane Equalization Control register of a Secondary PCI Express Extended Capability structure, a 16.0 GT/s Lane Equalization Control register of a Physical Layer 16.0 GT/s Extended Capability structure, a Virtual Channel Capability structure of all registers, all registers of a Multi-Function Virtual Channel Capability structure, all registers of a Data Link Feature Extended Capability structure, all registers of a Physical Layer 16.0 GT/s Extended Capability structure, and all registers of Lane Margining of a Receiver Extended Capability structure.

Controls that enable the functions Function 0 to Function N to initiate requests on PCI express may be cleared, including Bus Master Enable, MSI interrupt enable, and the like, effectively causing the functions Function 0 to Function N to become quiescent on the link.

Port state machines associated with link functionality including those in the physical and data link layers may not be reset by FLR, and VC0 may remain initialized following an FLR. Any outstanding INTx interrupt asserted by the functions Function 0 to Function N may be deasserted by sending the corresponding Deassert_INTx Message prior to starting the FLR.

When the FLR is initiated to the functions Function 0 to Function N of the PCIe device 400, if another Function continues to assert a matching INTx, no Deassert_INTx Message will be transmitted.

After an FLR has been initiated by writing a 1 b to the Initiate Function Level Reset bit, the functions Function 0 to Function N must complete the FLR within 100 ms. If software initiates an FLR when the transactions pending bit is 1 b, then software must not initialize the functions Function 0 to Function N until allowing adequate time for any associated Completions to arrive, or to achieve reasonable certainty that any remaining completions will never arrive. Thus, the computing system may allow as much time as provided by the pre-FLR value for Completion Timeout. If completion timeouts are disabled on the functions Function 0 to Function N when the FLR is issued, then the delay may be system dependent but may be 100 ms or more. When a function ready status is implemented, a computing system may issue a configuration request to the functions Function 0 to Function N right after receiving a function level reset message indicating that it is completely prepared for configuration.

Upon receipt of an FLR, the functions Function 0 to Function N may either clear all transaction statuses including Transactions Pending, or may set the Completion Timeout to its default value so that all pending transactions may time out during FLR execution. The transactions pending bit may be clear upon completion of the FLR.

Since FLR modifies Function state, the behavior of FLR may be specified using a set of criteria that, when applied to the Functions Function 0 to Function N, show that the functions Function 0 to Function N have them. The following criteria must be applied using Function-specific knowledge to evaluate the functions Function 0 to Function N's behavior in response to an FLR.

-   -   The function (Function 0 to Function N) may not give the         appearance of an initialized adapter with an active host on any         external interfaces controlled by the corresponding function         (Function 0 to Function N). The steps needed to terminate         activity on the external interfaces may be exceptional. For         example, a network adapter may not respond to queries that would         require adapter initialization by the host system or interaction         with an active host system, but may be permitted to perform an         action that it is designed to be perform without host         initialization or interaction. When the network adapter includes         multiple functions Function 0 to Function N that operate on the         same external network interface, this rule may affect only those         aspects associated with particular function reset by the FLR.     -   The functions Function 0 to Function N may not retain within         itself software readable state that potentially includes secret         information associated with any preceding use of the functions         Function 0 to Function N. Main host memory assigned to the         functions Function 0 to Function N may not be modified by the         functions Function 0 to Function N. For example, a function         (Function 0 to Function N) with internal memory readable         directly or indirectly by host software may clear or randomize         that memory.     -   The function (Function 0 to Function N) may return to a state         such that normal configuration of the function (Function 0 to         Function N)'s PCI Express interface may cause it to be useable         by drivers normally associated with the functions Function 0 to         Function N.

When an FLR is initiated, the targeted functions Function 0 to Function N must behave as follows:

-   -   The functions Function 0 to Function N may return the completion         for the configuration write that initiates the FLR operation,         and may then initiate the FLR.     -   While the FLR is in progress, when a request arrives, the         request may be permitted to be silently discarded without         logging or signaling it as an error. In addition, if a         completion arrives, the completion may be permitted to be         handled as an unexpected completion or to be silently discarded         without logging or signaling it as an error.

When the function (Function 0 to Function N) is required to complete the FLR operation within a time limit, a subsequent function-specific initialization sequence may require an additional time. When the additional time is required, the function (Function 0 to Function N) may return a configuration request retry status (CRS) completion status when a configuration request is received after the time limit. After the function (Function 0 to Function N) responds to the configuration request with a completion status other than CRS, it may not be permitted to return the CRS until it is reset again.

FIG. 5 illustrates an example of a single root input/output virtualization (SR-IOV) capable PCIe device 500 according to an embodiment of the present disclosure.

The PCIe device 500 as shown in FIG. 5 may represent one of the PCIe device 2000 as shown in FIG. 1 and the PCIe devices 2000-1 to 2000-3 as shown in FIGS. 2 and 3.

For example, FIG. 5 may represent the PCIe device 500 to which SR-IOV capability is applied.

Referring to FIG. 5, the PCIe device 500 may include a physical function 0 PF0 and a plurality of virtual functions VF0_1 to VF0_N associated with the physical function 0 PF0. The virtual function 0, 1 VF0_1 may refer to a first virtual function that is associated with the physical function 0 PF0. In the same manner, the virtual function 0, N VF0_N may refer to an Nth virtual function that is associated with the physical function 0 PF0. According to an embodiment, the configuration space, the register setting process, the error handling operation, and the function level reset operation as described above with reference to FIG. 4 may apply to the physical function 0 PF0.

The physical function 0 PF0 may support SR-IOV capability. According to an embodiment, after a reset operation, the physical function 0 PF0 may disable the SR-IOV capability. To discover the page sizes supported by the physical function 0 PF0, and the plurality of virtual functions VF0_1 to VF0_N, Supported Page Sizes configuration field may be read.

The plurality of virtual functions VF0_1 to VF0_N may share a plurality of common configuration space fields with the physical function 0 PF0. Sharing may reduce the hardware resource requirements to implement the plurality of virtual functions VF0_1 to VF0_N. For example, the plurality of virtual functions VF0_1 to VF0_N may use the same configuration mechanisms and header types as the physical function 0 PF0. In addition, the plurality of virtual functions VF0_1 to VF0_N may share a VF BAR set. In addition, the plurality of virtual functions VF0_1 to VF0_N may share a VF memory space enable (MSE) bit that controls access to VF memory space. In other words, when the VF MSE bit is cleared, the memory mapped space allocated for all virtual functions VF0_1 to VF0_N may be disabled.

The InitialVFs and TotalVFs fields included in the SR-IOV capability may be used to discover the maximum number of virtual functions that may be associated with the physical function 0 PF0. For example, when the PCIe device 500 does not support VF migration, TotalVFs and InitialVFs may contain the same value. On the other hand, when the PCIe device 500 supports VF migration, if TotalVFs is read, the physical function 0 PF0 may return the number of virtual functions that may be assigned to the physical function 0 PF0. In addition, when InitialVFs is read, the physical function 0 PF0 may return the initial number of virtual functions assigned to the physical function 0 PF0.

The physical function 0 PF0 and the plurality of virtual functions VF0_1 to VF0_N may be assigned unique routing IDs. The Routing ID for each virtual function (VF0_1 to VF0_N) may be determined using the routing ID of the physical function 0 PF0 and fields included in the SR-IOV capability of the physical function 0 PF0.

All PCIe and SR-IOV configuration access may be carried out through a trusted software component such as a virtualization intermediary or a single root PCI manager.

According to an embodiment, the physical function 0 PF0 and the plurality of virtual functions VF0_1 to VF0_N may contain physical resources including configuration space. Each virtual function (VF0_1 to VF0_N) may contain a non-shared set of physical resources required to deliver Function-specific services, e.g., resources such as work queues, data buffers, etc. These resources may be directly accessed by a system image without requiring intervention of the virtualization intermediary or the single root PCI manager.

One or more virtual functions VF0_1 to VF0_N may be assigned to each system image. The physical function 0 PF0 and the plurality of virtual functions VF0_1 to VF0_N may include ATC.

According to an embodiment, the physical function 0 PF0 may be used to manage device-specific functionality such as internal resource allocation to each virtual function (VF0_1 to VF0_N), VF arbitration to shared resources such as the PCIe Link or the Function-specific Link (e.g., a network or storage Link), etc.

According to an embodiment, the configuration space of the physical function 0 PF0 may include the SR-IOV extended capability. For example, the SR-IOV extended capability may include an SR-IOV Extended Capability Header register, an SR-IOV Capabilities register, an SR-IOV Control register, an SR-IOV Status register, an InitialVFs register, a TotalVFs register, a NumVFs register, a Function Dependency Link register, a First VF Offset register, a VF Stride register, a VF Device ID register, a Supported Page Sizes register, a System Page Size register, a VF BAR0, VF BAR1, . . . , a VF BAR5 register, and a VF Migration State Array Offset register.

The SR-IVO control register may include a virtual function (VF) Enable field.

Virtual function enable may manage the assignment of the plurality of virtual functions VF0_1 to VF0_N with respect to the associated physical function 0 PF0. When the virtual function Enable is set, the plurality of virtual functions VF0_1 to VF0_N associated with the physical function 0 PF0 may be accessible in the PCI Express fabric. When the virtual function enable is set, the virtual functions VF0_1 to VF0_N may respond to and issue PCI Express transactions following rules for PCI Express Endpoint Functions.

When the virtual function enable is clear, the plurality of virtual functions VF0_1 to VF0_N may be disabled and may not be visible in the PCI Express fabric. Requests to these virtual functions VF0_1 to VF0_N may receive Unsupported Request (UR) and may not issue PCI Express transactions.

To allow components to perform internal initialization, after changing the virtual function enable bit from 0 to 1, the system may not be permitted to issue requests to the virtual functions VF0_1 to VF0_N which are enabled by the corresponding VF Enable bit until one of the following is true: At least 100 ms has passed; an FRS message has been received from the physical function 0 PF0 with a reason code of the virtual function Enabled; and at least VF Enable time has passed. The VF Enable time may be either a reset time value in the readiness time reporting capability associated with the virtual functions VF0_1 to VF0_N, or a value determined by system software/firmware.

The root complex and/or system software may allow at least 1.0 seconds after setting the VF Enable bit, before it may determine that the virtual function (VF0_1 to VF0_N) which fails to return a successful completion status for a valid configuration request is broken. After setting the VF Enable bit, the virtual functions VF0_1 to VF0_N enabled by the corresponding VF Enable bit may be permitted to return a CRS status to configuration requests up to the 1.0 s limit, when they are not ready to provide a successful completion status for a valid configuration request. After the physical function 0 PF0 transmits an FRS Message with a reason code of VF Enabled, no virtual functions VF0_1 to VF0_N associated with the corresponding physical function 0 PF0 is permitted to return CRS without an intervening VF disable or other valid reset conditions. After returning a successful completion to any request, the virtual functions VF0_1 to VF0_N may not be permitted to return CRS without an intervening VF disable or other valid reset conditions.

Since the virtual functions VF0_1 to VF0_N do not have an MSE bit (MSE in the virtual functions VF0_1 to VF0_N is controlled by the VF MSE bit in the SR-IOV capability in the physical function 0 PF0), it may be possible for software to issue a memory request before the virtual function (VF0_1 to VF0_N) is ready to handle the MSE bit. Therefore, Memory Requests may not be issued to the virtual functions VF0_1 to VF0_N until at least one of the following conditions has been met:

-   -   The virtual function (VF0_1 to VF0_N) has responded successfully         to a Configuration Request. (CRS is not returned).

After issuing an FLR to the VF, at least one of the following is true: (1) at least 1.0 s has passed since the FLR was issued, (2) the virtual functions VF0_1 to VF0_N support Function Readiness Status and, after the FLR is issued, an FRS Message from the virtual functions VF0_1 to VF0_N with a reason code for FLR Completed has been received, or (3) at least FLR time has passed since the FLR is issued. FLR Time may be the FLR Time value in the Readiness Time Reporting capability associated with the virtual functions VF0_1 to VF0_N or a value determined by system software/firmware.

After setting VF Enable in the physical function 0 PF0, at least one of the following is true: (1) at least 1.0 s has passed since the VF Enable was set, (2) the physical function 0 PF0 supports Function Readiness Status and, after VF Enable is set, an FRS message from the physical function 0 PF0 with the reason code for the virtual function enabled has been received, or (3) minimum virtual function enable time has passed after the virtual function Enable is set. The virtual function enable time may be a reset time value in the Readiness Time Reporting capability associated with the virtual functions VF0_1 to VF0_N or a value determined by system software/firmware.

The virtual functions VF0_1 to VF0_N may be permitted to silently drop memory requests after an FLR is issued to the virtual functions VF0_1 to VF0_N or VF Enable has been set in the associated physical function 0 PF0 in the SR-IOV capability until the virtual functions VF0_1 to VF0_N respond successfully (without returning CRS) to any request.

Clearing VF Enable may effectively destroy the virtual functions VF0_1 to VF0_N. Setting VF Enable may effectively create the virtual functions VF0_1 to VF0_N. Setting VF Enable after it has previously been cleared may result in a new set of virtual functions VF0_1 to VF0_N. When the physical function 0 PF0 is in a D0 power state, the new virtual functions VF0_1 to VF0_N may be in the D0_(uninitialized) state. If the physical function 0 PF0 is in a lower power state, a behavior may be undefined

When VF Enable is clear, the physical function 0 PF0 that supports FRS may send an FRS Message with FRS Reason VF Disabled to indicate when this operation has been completed. The physical function 0 PF0 may not be permitted to send this message when there are outstanding non-posted requests issued by the physical function 0 PF0 or any of the virtual functions VF0_1 to VF0_N associated with the physical function 0 PF0. The FRS message may only be sent after these requests have been completed (or timed out).

When software Clears VF Enable, no field in the SR-IOV Extended Capability or the VF Migration State Array may be accessed until either:

-   -   At least 1.0 s has elapsed after VF Enable was cleared, or     -   The physical function 0 PF0 supports FRS and after VF enable was         cleared, an FRS Message has been received from the physical         function 0 PF0 with a reason code of VF Disabled.

InitialVFs registers may indicate to SR-PCIM the number of virtual functions VF0_1 to VF0_N that are initially associated with the physical function 0 PF0.

TotalVFs registers may indicate the maximum number of virtual functions VF0_1 to VF0_N that may be associated with the physical function 0 PF0.

NumVFs registers may control the number of virtual functions VF0_1 to VF0_N that are visible.

Virtual function base address registers may define base address registers (BARs) of the virtual functions VF0_1 to VF0_N. When the virtual function address register is written with an actual address value, and VF Enable and VF MSE are set, the BAR may map NumVFs BARs.

According to an embodiment, the configuration space of the physical function 0 PF0 and the virtual functions VF0_1 to VF0_N may include a type 0 configuration space header, a PCIe capability register, a PCI standard capability register, a PCIe extended capability register, and the like.

According to an embodiment, register field values included in the configuration space of the virtual functions VF0_1 to VF0_N may be subordinate to or independent from register field values included in the configuration space of the physical function 0 PF0. For example, the register field values included in the configuration space of the virtual functions VF0_1 to VF0_N may have a value of 0 (zero) when they are subordinate to the register field values included in the configuration space of the physical function 0 PF0. The virtual functions VF0_1 to VF0_N may perform a configuration operation according to the register field values of the associated physical function 0 PF0.

According to an embodiment, the plurality of virtual functions VF0_1 to VF0_N may perform an error handling operation. For example, when the physical function 0 PF0 handles an error using advanced error reporting, the virtual functions VF0_1 to VF0_N may also handle an error using advanced error reporting.

According to an embodiment, the plurality of virtual functions VF0_1 to VF0_N may perform a reset operation.

For example, the virtual functions VF0_1 to VF0_N may complete internal initialization when one of the following occurs:

-   -   The virtual function (VF0_1 to VF0_N) has responded successfully         to a configuration request (CRS is not returned).     -   After issuing a function level reset to the virtual functions         VF0_1 to VF0_N, one of the following is true: (1) at least 1.0 s         has passed, (2) an FRS message from the virtual functions VF0_1         to VF0_N with a reason code FLR completed has been received,         or (3) minimum FLR time has passed. The function level reset         time may be a function level reset time value in the Readiness         Time Reporting capability associated with the virtual functions         VF0_1 to VF0_N or a value determined by system         software/firmware.     -   After setting VF Enable in the physical function 0 PF0, at least         one of the following may be true: (1) at least 1.0 s has passed         since VF Enabled was set, or (2) after VF Enabled was set, an         FRS Message has been received from the physical function 0 PF0         with a reason code of VF enabled.

FIG. 6 illustrates another example (a PCIe device 600) of a PCIe device using SR-IOV according to an embodiment of the present disclosure.

The PCIe device 600 as shown in FIG. 6 may correspond to the PCIe device 2000 as shown in FIG. 1 or one of the PCIe devices 2000-1 to 2000-3 as shown in FIGS. 2 and 3.

For example, FIG. 6 may represent the PCIe device 600 to which SR-IOV capability is applied.

The PCIe device 600 provides a plurality of physical functions PF0 to PFM and a plurality of virtual functions VF0_1 to VFM_K associated with the plurality of physical functions PF0 to PFM. According to an embodiment, the configuration space, the register setting process, the error handling operation, and the function level reset operation as described above with reference to FIG. 4 may apply to the plurality of physical functions PF0 to PFM. In addition, the configuration space described with reference to physical function 0 PF0 of FIG. 5 may apply to the plurality of physical functions PF0 to PFM. In addition, the configuration space, the error handling operation, and the reset operation described with respect to the virtual functions VF0_1 to VF0_N of FIG. 5 may apply to the plurality of virtual functions VF0_1 to VFM_K.

The plurality of physical functions PF0 to PFM may include SR-IOV capability, and zero (0) or more virtual functions may apply to the plurality of physical functions PF0 to PFM. The number of virtual functions assigned to each physical function may vary.

When ARI capability is supported, the plurality of physical functions PF0 to PFM and the plurality of virtual functions VF0_1 to VFM_K may be assigned to function groups.

According to an embodiment, the plurality of physical functions PF0 to PFM may be of the same device type. For example, the plurality of physical functions PF0 to PFM may provide the same network device or the same storage device functionality.

According to an embodiment, the plurality of physical functions PF0 to PFM may indicate different device types. For example, one of the plurality of physical functions PF0 to PFM may represent a network device, and another of the physical functions PF0 to PFM may represent an encryption device.

In situations where there is a usage model dependency between device types (such as for each virtual function that is a network device type, each system image also requires a virtual function that is an encryption device type) the SR-IOV capability may provide a process to indicate these dependencies. The number of physical functions and the number of virtual functions may vary based on usage model requirements.

According to an embodiment, using the Alternative Routing Identifier (ARI) capability, the PCIe device 600 may support up to 256 physical functions. Function Number assignment may be implementation specific. The physical functions PF0 to PFM may only be associated with the PCIe device 600's captured bus number. The PCIe device 600 that may use SR-IOV capability may consume two or more bus numbers. The physical functions PF0 to PFM may be associated with any bus number (the captured Bus Number plus any additional bus numbers configured by software) within a bus number range of the PCIe device 600. Use of multiple bus numbers may enable the PCIe device 600 to support a very large number of virtual functions (up to the size of the routing ID space minus the bits used to identify intervening busses). When software does not configure sufficient additional bus numbers, then the virtual functions implemented for the additional bus numbers may not be visible.

Recently, there is an increasing demand for multi-function products for directly connecting a host and a PCIe device and 1:1 mapping between a system image and a function of the PCIe device. Examples of kinds of the multi-function products may include a multi-function device including a plurality of physical functions and an SR-IOV capable device. A multi-function device may not suffer performance degradation but may have weak security. In addition, an SR-IOV capable device may have strong security but suffer performance degradation. Therefore, every user may require different PCIe device types. A user may request that one PCIe device use both multi-function and virtual function. Therefore, in an embodiment of the present disclosure, a PCIe device including common functions operating in various function types may be shown.

FIG. 7 illustrates a PCIe device 700 according to an embodiment of the present disclosure.

Referring to FIG. 7, the PCIe device 700 may include a function type controller 710, a default physical function 720, and a plurality of common functions 730-1 to 730-n. The PCIe device 700 may correspond to the PCIe device 2000 as shown in FIG. 1 or to one of the PCIe devices 2000-1 to 2000-3 as shown in FIGS. 2 and 3.

The function type controller 710 may determine function types of a plurality of common functions 730-1 to 730-n according to function type setting information SET_INFO.

According to an embodiment, the function type controller 710 may determine one of the plurality of function types for a function type of each of the common functions 730-1 to 730-n. The plurality of function types may include a physical function type, a virtual function type, and a disable function type in which operations are disabled. The function type controller 710 may determine the respective function type of each of the common functions 730-1 to 730-n as one of the physical function type, the virtual function type and the disable function type.

The function type setting information SET_INFO may indicate a respective function type to be set to each of the common functions 730-1 to 730-n. For example, the function type setting information SET_INFO may include at least one of the number of common functions to be configured as a physical function type, the number of common functions to be configured as a virtual function type, the number of common functions to be configured as a disable function type, among the plurality of common functions 730-1 to 730-n, and function type mapping information indicating a mapping relationship between each of the plurality of common functions 730-1 to 730-n and a respective function type. The function type setting information SET_INFO may be provided from the host 1000, or may be stored in advance in firmware included in the PCIe device 700 during the manufacturing process of the PCIe device 700.

In an embodiment, the function type controller 710 may receive the function type setting information SET_INFO from the host 1000. For example, the host 1000 may provide the function type setting information SET_INFO to the function type controller 710 by using a technology such as a vendor-specific capability message, a vendor-defined capability, a new PCIe capability defined by a user, Management Component Transport Protocol (MCTP) over System Manager bus (SMbus), MCTP over PCIe, or the like.

According to an embodiment, the function type controller 710 may generate a function type control signal FT_CSIG based on the function type setting information SET_INFO. The function type control signal FT_CSIG may be provided to determine the function types of the common functions 730-1 to 730-n and cause the common functions 730-1 to 730-n to operate according to the determined function types. The function type controller 710 may provide the function type control signal FT_CSIG to the plurality of common functions 730-1 to 730-n to determine the function types of the plurality of common functions 730-1 to 730-n.

According to an embodiment, after the function type of each of the plurality of common functions 730-1 to 730-n is determined, the function type controller 710 may provide the host 1000 with the determined function type information CF_INFO of the plurality of common functions 730-1 to 730-n.

According to an embodiment, the function type controller 710 may change the function type of a common function which is configured as a physical function type into a virtual function type based on the function type setting information SET_INFO. In addition, the function type controller 710 may change the function type of a common function which is configured as a virtual function type into a physical function type based on the function type setting information SET_INFO.

For example, after the function type controller 710 resets the plurality of common functions 730-1 to 730-n in the next link up operation, then based on the function type setting information SET_INFO, the function type controller 710 may change the function type of a common function which is configured on reset as a physical function type into a virtual function type, or may change the function type of a common function configured on reset as a virtual function type into a physical function type.

The default physical function 720 may be a PCIe function. The default physical function 720 may have the same configuration as the zeroth function Function 0 as described above with reference to FIG. 4, or the physical function 0 PF0 as described above with reference to FIGS. 5 and 6.

The plurality of plurality of common functions 730-1 to 730-n may be PCIe functions.

According to an embodiment, the plurality of common functions 730-1 to 730-n may be an independent operation unit for providing physical resources included in the PCIe device 700. Each of the plurality of common functions 730-1 to 730-n may be allocated some of the physical resources included in the PCIe device 700. The plurality of common functions 730-1 to 730-n may be mapped to the system images of the host 1000 and provide the allocated physical resources to the system images.

According to an embodiment, the plurality of common functions 730-1 to 730-n may perform operations associated with a PCIe interface according to the determined function types. The operations associated with the PCIe interface may include a data processing operation of receiving a command from the host 1000 and providing the host 1000 with a response to the command, an error handling operation of detecting an error and reporting the detected error, a power management operation of managing the power of a function, and a reset operation.

Therefore, according to an embodiment of the present disclosure, by providing a PCIe device including a plurality of common functions operating according to respective determined function types, a PCIe device gate count may be reduced to minimize power consumption and device size.

FIG. 8 illustrates a common function 800 according to an embodiment of the present disclosure.

The common function 800 as shown in FIG. 8 may correspond to one of the plurality of common functions 730-1 to 730-n as shown in FIG. 7. Therefore, a description with reference to FIG. 8 may apply to the plurality of common functions 730-1 to 730-n as shown in FIG. 7. In addition, the function type controller 710 shown in FIG. 8 may indicate the function type controller 710 shown in FIG. 7.

Referring to FIG. 8, the common function 800 may include a configuration space 810, an operation controller 820, and a multiplexer (MUX) 830.

The configuration space 810 may include registers for configuring the common function 800 to perform operations associated with a PCIe interface. For example, the common function 800 may perform operations based on information in the configuration space 800. More specifically, the common function 800 may perform operations based on field values of the registers included in the configuration space 810.

According to an embodiment, the configuration space 810 may include information on capabilities available in the common function 800.

According to an embodiment, the function type controller 710 may determine function types of the plurality of common functions 800 by changing the values of the registers included in the configuration space 810 according to the function type setting information SET_INFO.

For example, the function type controller 710 may provide the function type control signal FT_CSIG to the configuration space 810 and change the values of the registers included in the configuration space 810 according to the determined function type. The configuration space 810 may enable registers associated with the determined function type and disable registers not associated with the determined function type. The function type controller 710 may perform clock gating on the disabled registers among the registers included in the configuration space 810.

The operation controller 820 may control the plurality of common functions 800 to perform operations associated with a PCIe interface according to the determined function type. The operation controller 820 may control operations of the common function 800 based on the field values of the enabled registers in the configuration space 810.

The MUX 830 may provide the operation controller 820 with one of the signals externally received based on the determined function type. For example, the function type controller 710 may provide the MUX 830 with the function type control signal FT_CSIG. The MUX 830 may operate based on the determined function type indicated by the function type control signal FT_CSIG.

According to an embodiment, the MUX 830 may provide the operation controller 820 with one of the externally received signals based on the field values of the registers included in the configuration space 810. The MUX 830 may receive a host signal H_SIG from the host 1000 and a physical function signal PF_SIG from a physical function. The host signal H_SIG and the physical function signal PF_SIG may correspond to the operations associated with the PCIe interface. The physical function signal PF_SIG may be provided by the default physical function 720 or another common function having a physical function type.

For example, when the function type of the common function 800 is determined as a physical function type, the common function 800 may operate in a subordinate manner to the default physical function 720, or in an independent manner depending on information included in the configuration space 810. The MUX 830 may receive the physical function signal PF_SIG corresponding to the operation subordinate to the default physical function 720 from the default physical function 720, and may provide the physical function signal PF_SIG to the operation controller 820. In addition, the MUX 830 may receive the host signal H_SIG corresponding to the independent operation from the host 1000 and provide the host signal H_SIG to the operation controller 820.

For example, when the function type of the common function 800 is determined as a virtual function type, the common function 800 may operate in a subordinate manner to the default physical function 720 or another common function having a physical function type, or in an independent manner based on the information included in the configuration space 810. The MUX 830 may receive the physical function signal PF_SIG corresponding to the subordinate operation from the default physical function 720 or another common function, and may provide the physical function signal PF_SIG to the operation controller 820. In addition, the MUX 830 may receive the host signal H_SIG corresponding to the independent operation from the host 1000 and provide the same to the operation controller 820.

FIG. 9 illustrates a layout of a configuration space according to an embodiment of the present disclosure.

FIG. 9 may be a diagram showing a layout of the configuration space 810 as shown in FIG. 8.

Referring to FIG. 9, the configuration space 810 may include a plurality of capability registers CAP 1 to CAP 4. Although FIG. 9 shows only four capability registers CAP 1 to CAP 4, more or less than four capability registers may be included in the configuration space 810 according to embodiments. According to an embodiment, the capability may be a PCIe capability.

According to an embodiment, the function type controller 710 may enable capabilities associated with function types determined for the plurality of common functions 800 based on pointer values among register values included in the configuration space 810, the pointer values indicating enabled capabilities. In addition, according to an embodiment, the function type controller 710 may disable capabilities not associated with the function types determined for the plurality of common functions 800 based on the pointer values indicating the capabilities to be enabled.

For example, when the function type of the common function 800 is determined as a physical function type, the function type controller 710 may enable capabilities associated with the physical function type and disable capabilities not associated with the physical function type. In another example, when the function type of the common function 800 is determined as a virtual function type, the function type controller 710 may enable capabilities associated with the virtual function type and disable capabilities not associated with the physical function type. In another example, when the function type of the common function 800 is determined as a disable function type, the function type controller 710 may disable all capabilities.

According to an embodiment, capabilities may be enabled or disabled based on pointer values among the field values of the registers included in the configuration space 810. A pointer value may be an offset with respect to the configuration space 810 indicating a location of the next capability. When there is no next capability, the pointer value may be set to ooh.

For example, it may be assumed that the determined function type of the common function 800 is associated with a first capability register CAP 1, a second capability register CAP 2, and a fourth capability register CAP 4 and is not associated with a third capability register CAP 3. When the first capability register CAP 1 is enabled, a pointer value POINTER 1 may indicate a location of the second capability register CAP 2 which is the next capability register to be enabled. Thereafter, a pointer value POINTER 2 included in the second capability register CAP 2 may indicate a location of the fourth capability register CAP 4 which is the next capability register to be enabled. The third capability register CAP 3 may be disabled since the pointer value POINTER 2 skips the third capability register CAP 3 and indicates the fourth capability register CAP 4. The third capability register CAP 3 may be hidden. When there is no next capability to be enabled, a pointer value POINTER 3 included in the fourth capability register CAP 4 may be set to 00h.

According to an embodiment, the function type controller 710 may perform clock gating on a disabled capability register.

FIG. 10 illustrates an example (a PCIe device 700A) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700A as shown in FIG. 10 may be an example of a PCIe device configured as a multi-function device. That is, FIG. 10 shows an example in which the function type of each of the common functions 730-1 to 730-n included in the PCIe device 700A is configured as a physical function type. Therefore, the PCIe device 700A shown in FIG. 10 may operate in the same manner as the multi-function PCIe device 400 described above with reference to FIG. 4.

Referring to FIG. 10, the function type controller 710 may provide the physical function type control signal PFT_CSIG to each of the plurality of common functions 730-1 to 730-n. The physical function type control signal PFT_CSIG may be a control signal for configuring the function type of each of the common functions 730-1 to 730-n as a physical function type. As a result, the function type of each of the plurality of common functions 730-1 to 730-n may be configured as a physical function type. The plurality of common functions 730-1 to 730-n may perform operations associated with a PCIe interface according to the physical function type. In other words, the common functions 730-1 to 730-n may respectively operate like physical functions.

The common functions 730-1 to 730-n each of which is configured as the physical function type may perform operations based on the base address registers (BARs) included in the configuration space of each of the common functions 730-1 to 730-n. According to an embodiment, a base address register may determine the amount of a system memory space necessary for a function and provide a base address for mapping with respect to a function memory space. The base address registers may be mapped to a memory space or an I/O space. For example, the common functions 730-1 to 730-n may have independent addresses through the base address registers and provide addresses to be used when performing operations through the base address registers.

According to an embodiment, the plurality of common functions 730-1 to 730-n may perform PCIe associated operations based on registers corresponding to PCIe associated operations included in the configuration space of the plurality of common functions 730-1 to 730-n, respectively. For example, an error handling operation may be performed based on registers which are associated with the error handling operation and included in the configuration space of each of the common functions 730-1 to 730-n. For example, a power management operation may be performed based on registers which are associated with the power management operation and included in the configuration space of each of the common functions 730-1 to 730-n. In other words, the common functions 730-1 to 730-n each of which is determined as a physical function type may perform operations in an independent manner based on information in their respective configuration spaces.

According to an embodiment, the plurality of common functions 730-1 to 730-n may perform operations based on the information in configuration space of the default physical function 720. In other words, the plurality of common functions 730-1 to 730-n may perform operations based on information in the configuration space of the default physical function 720. For example, management of the link, PCIe functionality shared by the plurality of common functions 730-1 to 730-n, and error reporting in a physical layer may be carried out based on information in the configuration space of the default physical function 720.

According to an embodiment, each common function of the plurality of common functions 730-1 to 730-n may perform a respective reset operation in response to a reset request for that common function from the host 1000, which will be described below in more details with reference to FIG. 16A.

FIG. 11 illustrates another example (a PCIe device 700B) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700B as shown in FIG. 11 may be an example of an SR-IOV capable device. That is, FIG. 11 shows an example in which a function type of each of the common functions 730-1 to 730-n included in the PCIe device 700B is determined as a physical function type. Therefore, the PCIe device 700B as shown in FIG. 11 may operate in the same manner as the PCIe device 500 as described above with reference to FIG. 5.

Referring to FIG. 11, the function type controller 710 may provide a virtual function type control signal VFT_CSIG to the plurality of common functions 730-1 to 730-n. The virtual function type control signal VFT_CSIG may be a control signal for determining the function type of each of the common functions 730-1 to 730-n as a virtual function type. As a result, each of the plurality of common functions 730-1 to 730-n may be configured as the virtual function type. The plurality of common functions 730-1 to 730-n may perform operations associated with a PCIe interface according to the virtual function type. In other words, the common functions 730-1 to 730-n may respectively operate like virtual functions.

The plurality of common functions 730-1 to 730-n each of which is configured as the virtual function type may be associated with the default physical function 720. According to an embodiment, the default physical function 720 may be an SR-IOV capability enabled function. The function type controller 710 may provide virtual function information VF_INFO to the associated default physical function 720. The virtual function information VF_INFO may include identification information of common functions operating as a virtual function type, the number of common functions, and a routing ID offset indicating the next common function of the virtual function type.

The default physical function 720 may modify registers included in the configuration space of the default physical function 720 based on the virtual function information VF_INFO. According to an embodiment, the default physical function 720 may enable or disable the plurality of common functions 730-1 to 730-n based on a virtual function (VF) enable value included in the register of the SR-IOV capability. For example, when the virtual function enable included in the register of the SR-IOV capability is set, the plurality of registers of the common functions 730-1 to 730-n may be enabled. In another example, when the virtual function enable included in the register of the SR-IOV capability is clear, the plurality of common functions 730-1 to 730-n may be disabled.

The common functions 730-1 to 730-n each of which is configured as the virtual function type may perform operations based on base address registers (BARs) included in a configuration space of a function associated with the common functions 730-1 to 730-n. For example, when the common functions 730-1 to 730-n are each associated with the default physical function 720, the common functions 730-1 to 730-n may perform operations based on the base address registers (BARs) included in the configuration space of the default physical function 720. In other words, the plurality of common functions 730-1 to 730-n each of which is configured as the virtual function type may not have independent base addresses and may perform operations through a base address of the associated default physical function 720.

According to an embodiment, the plurality of common functions 730-1 to 730-n may perform PCIe interface associated operations based on registers corresponding to the PCIe interface associated operations included in the configuration space of the associated function. For example, when associated with the default physical function 720, the plurality of common functions 730-1 to 730-n may perform the PCIe interface associated operations based on the registers included in the configuration space of the default physical function 720. For example, the common functions 730-1 to 730-n may perform an error handling operation based on registers which are associated with the error handling operation and included in the configuration space of the default physical function 720. For example, the common functions 730-1 to 730-n may perform a power management operation based on registers associated with the power management operation included in the configuration space of the default physical function 720. In other words, the common functions 730-1 to 730-n each of which is configured as the virtual function type may perform some operations based on the configuration space of the associated function.

According to an embodiment, each of the plurality of common functions 730-1 to 730-n may perform operations based on the configuration space thereof. In other words, each of the plurality of common functions 730-1 to 730-n may perform some exceptional operations in an independent manner based on the configuration space thereof. For example, such as the case in which a register value of a configuration space is set to perform a power management operation in an independent manner, each of the plurality of common functions 730-1 to 730-n may perform some operations based on the configuration space thereof.

According to an embodiment, each common function of the plurality of common functions 730-1 to 730-n may perform a reset operation in response to at least one of a reset request for an associated function of that common function as provided from the host 1000, a reset request for that common functions, and a clear operation of a virtual function enable value of the associated function. This will be described below in more details with reference to FIGS. 16B to 16D.

FIG. 12 illustrates another example (a PCIe device 700C) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700C as shown in FIG. 12 may be another example of an SR-IOV capable device. In the example of FIG. 12, respective function types of a first subset of the common functions 730-1 to 730-n included in the PCIe device 700C may be determined as a physical function type, respective function types of a second subset of the common functions 730-1 to 730-n may be determined as a virtual function type, and respective function types of a third subset of the common functions 730-1 to 730-n may be determined as a disable function type. Therefore, the PCIe device 700C as shown in FIG. 12 may operate in the same manner as the PCIe device 600 as described above with reference to FIG. 6.

Referring to FIG. 12, the function type controller 710 may provide a physical function type control signal PFT_CSIG to the first subset of common functions (common functions 730-1, 730-2, 730-3, and 730-n) among the plurality of common functions 730-1 to 730-n. In addition, the function type controller 710 may provide the virtual function type control signal VFT_CSIG to the second subset of common functions (common functions 730-4 and 730-5). In addition, the function type controller 710 may provide a disable function type control signal DFT_CSIG to the third subset of common functions (common function 730-6). The disable function type control signal DFT_CSIG may be a control signal for determining the function type of the common function 6 730-6 as a disable function type. Therefore, the function type of each of the common functions 730-1, 730-2, 730-3, and 730-n may be determined as a physical function type, the function type of each of the common functions 730-4 and 730-5 may be determined as a virtual function type, and the function type of the common function 6 730-6 may be determined as a disable function type.

The common functions 730-1, 730-2, 730-3, and 730-n may operate in the same manner as the plurality of common functions 730-1 to 730-n each of which is configured as the physical function type as described above with reference to FIG. 10. The common functions 730-4 and 730-5 may operate in the same manner as the plurality of common functions 730-1 to 730-n each of which is configured as the virtual function type as described above with reference to FIG. 11.

According to an embodiment, the common functions 730-4 and 730-5 each of which is configured as the virtual function type may be associated with the common functions 3 730-3 configured as the physical function type. According to an embodiment, the common function 3 730-3 may be an SR-IOV capability enabled function. The function type controller 710 may provide the virtual function information VF_INFO to the associated common function 3 730-3. The virtual function information VF_INFO may include identification information of common functions operating as a virtual function type, the number of common functions, a routing ID offset indicating the next common function of a virtual function type, a first virtual function offset, a virtual function stride, and the like. The first virtual function offset may indicate an identification information offset, relative to the associated physical function, of the first common function among the common functions determined as the virtual function type. The virtual function stride may indicate an identification information offset among the common functions determined as the virtual function type. The virtual function information VF_INFO may include information for setting the first virtual function offset to ‘1’ and the virtual function stride to ‘1’.

According to an embodiment, the common function 3 730-3 may modify the registers included in the configuration space of the common function 3 730-3 based on the virtual function information VF_INFO. According to an embodiment, the common function 3 730-3 may enable or disable the common functions 730-4 and 730-5 based on a virtual function (VF) enable value included in the register of the SR-IOV capability. For example, when the virtual function enable included in the register of the SR-IOV capability of the common function 3 730-3 is set, the common functions 730-4 and 730-5 may be enabled. In another example, when the virtual function enable included in the register of the SR-IOV capability of the common function 3 730-3 is clear, the common functions 730-4 and 730-5 may be disabled. In addition, the common function 3 730-3 may store the first virtual function offset included in the register of the SR-IOV capability as ‘1’ and the virtual function stride as ‘1’ based on the virtual function information VF_INFO.

The common functions 730-4 and 730-5 each of which is determined the virtual function type may perform operations based on the base address register included in the configuration space of the associated common function 3 730-3. For example, the common functions 730-4 and 730-5 may perform operations based on the base address register included in the configuration space of the associated common function 3 730-3. In other words, the common functions 730-4 and 730-5 may not have independent base addresses and may perform operations through the base address of the associated common function 3 730-3.

According to an embodiment, the plurality of common functions 730-4 and 730-5 may perform PCIe interface associated operations based on registers corresponding to the PCIe interface associated operations included in the configuration space of the associated function. For example, the common functions 730-4 and 730-5 may perform PCIe interface associated operations based on the registers included in the configuration space of the associated common function 3 730-3. For example, the common functions 730-4 and 730-5 may perform an error handling operation based on registers which are associated with the error handling operation and included in the configuration space of the common function 3 730-3. For example, the common functions 730-4 and 730-5 may perform a power management operation based on registers which are associated with the power management operation and included in the configuration space of the common function 3 730-3. In other words, the common functions 730-4 and 730-5 each of which is configured as the virtual function type may perform some operations based on the configuration space of the associated function.

According to an embodiment, the common functions 730-4 and 730-5 may perform operations based on the configuration space thereof. In other words, each of the common functions 730-4 and 730-5 may independently perform some exceptional operations based on the configuration space thereof. For example, such as in the case where a register value of a configuration space is set to perform a power management operation in an independent manner, the common functions 730-4 and 730-5 may perform some operations based on the configuration space thereof.

According to an embodiment, the function type controller 710 may disable registers included in the configuration space of the common function 6 730-6 configured as the disable function type. In addition, the function type controller 710 may perform clock gating the disabled registers in the configuration space of the common function 6 730-6.

FIG. 13 illustrates another example (a PCIe device 700D) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700D as shown in FIG. 13 may be an example of an SR-IOV capable device. In other words, as shown in FIG. 13, a function type of each of a first subset of the common functions 730-1 to 730-n included in the PCIe device 700D may be determined as a physical function type, and a function type of each of a second subset of the common functions 730-1 to 730-n may be determined as a virtual function type. Therefore, the PCIe device 700D as shown in FIG. 13 may operate in the same manner as the PCIe device 600 as described above with reference to FIG. 6.

Referring to FIG. 13, the function type controller 710 may provide the physical function type control signal PFT_CSIG to the first subset of common functions (common functions 730-1, 730-2, 730-4, 730-6, and 730-n). Therefore, the function type of each of the common functions 730-1, 730-2, 730-4, 730-6, and 730-n may be determined as a physical function type. In addition, the function type controller 710 may provide the virtual function type control signal VFT_CSIG to the second subset of common functions (common functions 730-3 and 730-5). Therefore, the function type of each of the common functions 730-3 and 730-5 may be determined as a virtual function type.

According to an embodiment, the common function 3 730-3 configured as the virtual function type may be associated with the default physical function 720, and the common function 5 730-5 configured as the virtual function type may be associated with the common function 2 730-2 configured as the physical function type. According to an embodiment, the default physical function 720 and the common function 2 730-2 may be SR-IOV capability enabled functions. The function type controller 710 may provide the virtual function information VF_INFO to the default physical function 720 and the common function 2 730-2. It may be assumed that the virtual function information VF_INFO includes information for setting the first virtual function offset to ‘3’.

According to an embodiment, the default physical function 720 and the common function 2 730-2 may modify the registers included in the configuration spaces of the default physical function 720 and the common function 2 730-2 based on the virtual function information VF_INFO. According to an embodiment, the default physical function 720 may enable or disable the common function 3 730-3 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. The common function 2 730-2 may enable or disable the common function 5 730-5 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. In addition, the default physical function 720 and the common function 2 730-2 may store the first virtual function offset included in the register of the SR-IOV capability as ‘1’ based on the virtual function information VF_INFO.

Operations of the common functions each of which is configured as the virtual function type as described above with reference to FIG. 12 may apply to the common function 3 730-3 and the common function 5 730-5.

FIG. 14 illustrates another example (a PCIe device 700E) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700E as shown in FIG. 14 may be an example of an SR-IOV capable device. In other words, as shown in the example of FIG. 14, a function type of each of a first subset of the common functions 730-1 to 730-n included in the PCIe device 700E may be determined as a physical function type, and a function type of each of a second subset of the common functions 730-1 to 730-n may be determined as a virtual function type. Therefore, the PCIe device 700E as shown in FIG. 14 may operate in the same manner as the PCIe device 600 as described above with reference to FIG. 6.

Referring to FIG. 14, the function type controller 710 may provide the physical function type control signal PFT_CSIG to the first subset of common functions (common functions 730-2, 730-4, 730-6, and 730-n). Therefore, the function type of each of the common functions 730-2, 730-4, 730-6, and 730-n may be determined as a physical function type. In addition, the function type controller 710 may provide the virtual function type control signal VFT_CSIG to the second subset of common functions (common functions 730-1, 730-3, and 730-5). Therefore, the function type of each of the common functions 730-1, 730-3, and 730-5 may be determined as a virtual function type.

According to an embodiment, the common functions 730-1, 730-3, and 730-5 each of which is configured as the virtual function type may be associated with the default physical function 720. According to an embodiment, the default physical function 720 may be an SR-IOV capability enabled function. The function type controller 710 may provide the virtual function information VF_INFO to the default physical function 720. The virtual function information VF_INFO may include information for setting the first virtual function offset to ‘1’ and the virtual function stride to ‘2’.

According to an embodiment, the default physical function 720 may modify registers included in the configuration space of the default physical function 720 based on the virtual function information VF_INFO. According to an embodiment, the default physical function 720 may enable or disable the associated common functions 730-1, 730-3, and 730-5 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. In addition, the default physical function 720 may store the first virtual function offset included in the register of the SR-IOV capability as ‘1’ and the virtual function stride as ‘2’ based on the virtual function information VF_INFO.

Operations of the common functions each of which is determined as the virtual function type as described above with reference to FIG. 12 may apply to the common functions 730-1, 730-3, and 730-5 as shown in FIG. 14.

FIG. 15 illustrates another example (a PCIe device 700F) of a PCIe device according to an embodiment of the present disclosure.

The PCIe device 700F as shown in FIG. 15 may be an example of an SR-IOV capable device. In other words, as shown in FIG. 14, for example, a function type of each of a first subset of the common functions 730-1 to 730-n included in the PCIe device 700F may be determined as a physical function type, and a function type of each of a second subset of the common functions 730-1 to 730-n may be determined as a virtual function type. Therefore, the PCIe device 700F as shown in FIG. 15 may operate in the same manner as the PCIe device 600 as described above with reference to FIG. 6.

Referring to FIG. 15, the function type controller 710 may provide the physical function type control signal PFT_CSIG to the first subset of common functions (common functions 730-1, 730-2, 730-5, and 730-n) among the plurality of common functions 730-1 to 730-n. Therefore, the function type of each of the common functions 730-1, 730-2, 730-5, and 730-n may be determined as a physical function type. In addition, the function type controller 710 may provide the virtual function type control signal VFT_CSIG to second subset of common functions (common functions 730-3, 730-4, and 730-6). Therefore, the function type of each of the common functions 730-3, 730-4, and 730-6 may be determined as a virtual function type.

According to an embodiment, the common function 3 730-3 determined as the virtual function type may be associated with the common function 1 730-1, the common function 4 730-4 determined as the virtual function type may be associated with the common function 2 730-2, and the common function 6 730-6 determined as the virtual function type may be associated with the common function 5 730-5. According to an embodiment, the common function 1 730-1, the common function 2 730-2, and the common function 5 730-5 may be SR-IOV capability enabled functions. The function type controller 710 may provide the virtual function information VF_INFO to the common function 1 730-1, the common function 2 730-2, and the common function 5 730-5. In this example, the virtual function information VF_INFO provided to the common function 1 730-1 includes information for setting the first virtual function offset to ‘3’, and the virtual function information VF_INFO provided to the common function 2 730-2 and the common function 5 730-5 includes information for setting the first virtual function offset to ‘1’.

According to an embodiment, the common function 1 730-1, the common function 2 730-2, and the common function 5 730-5 may modify registers included in the configuration spaces of the common function 1 730-1, the common function 2 730-2, and the common function 5 730-5 based on the respective virtual function information VF_INFO. According to an embodiment, the common function 1 730-1 may enable or disable the common function 4 730-4 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. The common function 2 730-2 may enable or disable the common function 3 730-3 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. The common function 5 730-5 may enable or disable the common function 6 730-6 based on the virtual function (VF) enable value included in the register of the SR-IOV capability. In addition, the common function 1 730-1 may store the first virtual function offset included in the register of the SR-IOV capability as ‘3’ based on the virtual function information VF_INFO. The common function 2 730-2 and the common function 5 730-5 may store the first virtual function offset included in the register of the SR-IOV capability as ‘1’ based on the virtual function information VF_INFO.

Operations of the common functions each of which is determined as the virtual function type as described above with reference to FIG. 12 may apply to the common function 3 730-3, the common function 4 730-4, and the common function 6 730-6 as shown in FIG. 13.

Therefore, referring to FIGS. 10 to 15, according to various embodiments of the present disclosure, by freely determining the arrangements of functions configured in various types, PCIe devices applicable to various environments may be provided.

FIG. 16A illustrates an example of a reset operation according to an embodiment of the present disclosure.

The PCIe device 700A as shown in FIG. 16A may represent the PCIe device 700A as shown in FIG. 10.

Referring to FIG. 16, the PCIe device 700A may receive a reset command for the common function 1 730-1 from the host 1000. According to an embodiment, the reset command may be a function level reset command FLR_CMD.

The PCIe device 700A may perform function level reset on the common function 1 730-1 configured as a physical function type in response to the function level reset command FLR_CMD.

As a result, only the common function 1 730-1 may be reset, and the reset operation of the common function 1 730-1 may not affect the other common functions 730-2 to 730-n or the default physical function 720.

In the above example, the reset operation performed on the common function 1 730-1 has been described. However, the reset operation of the common function 1 730-1 may apply to the other common functions 730-2 to 730-n each of which is determined as the physical function type. In addition, the above-described reset operation of the common function 1 730-1 may apply to the common functions 730-1, 730-2, 730-3, and 730-n each of which is configured as physical function types in the PCIe device 700C of FIG. 12.

FIG. 16B illustrates another example of a reset operation according to an embodiment of the present disclosure.

The PCIe device 700B as shown in FIG. 16B may represent the PCIe device 700B as shown in FIG. 11.

Referring to FIG. 16B, the PCIe device 700B may receive a reset command for the common function 1 730-1 from the host 1000. According to an embodiment, the reset command may be the function level reset command FLR_CMD.

The PCIe device 700B may perform function level reset for the common function 1 730-1 configured as the virtual function type in response to the function level reset command FLR_CMD. As a result, only the common function 1 730-1 may be reset, and the reset operation of the common function 1 730-1 may not affect the other common functions 730-2 to 730-n or the default physical function 720.

In the above example, the reset operation performed on the common function 1 730-1 has been described. However, the reset operation of the common function 1 730-1 may apply to the other common functions 730-2 to 730-n each of which is determined as the virtual function type. In addition, the above-described reset operation of the common function 1 730-1 may apply to the common functions 730-4 and 730-5 each of which is configured as the virtual function type in the PCIe device 700C of FIG. 12.

FIG. 16C illustrates another example of a reset operation according to an embodiment of the present disclosure.

The PCIe device 700B as shown in FIG. 16C may represent the PCIe device 700B as shown in FIG. 11.

Referring to FIG. 16C, the PCIe device 700B may receive a reset command for the default physical function 720 from the host 1000. According to an embodiment, the reset command may be the function level reset command FLR_CMD.

The PCIe device 700B may perform function level reset for the default physical function 720 in response to the function level reset command FLR_CMD. In addition, the PCIe device 700B may perform function level reset on the common functions 730-1 to 730-n each of which is configured as the virtual function type and associated with the default physical function 720. In other words, the function level reset may be performed on the common functions 730-1 to 730-n associated with the default physical function 720 as well as the default physical function 720.

The reset operation of the above-described common functions 730-1 to 730-n and the associated default physical function 720 may apply to the common functions 730-4 and 730-5 each of which is configured as the virtual function type and the common function 730-3 configures as the associated physical function type as shown in the PCIe device 700C of FIG. 12.

FIG. 16D illustrates another example of a reset operation according to an embodiment of the present disclosure.

The PCIe device 700B as shown in FIG. 16D may represent the PCIe device 700B as shown in FIG. 11.

Referring to FIG. 16D, the PCIe device 700B may receive a VF enable clear command CMD for setting a virtual function enable value to ‘clear’ from the host 1000. The default physical function 720 may set the VF enable value included in the configuration space to ‘clear’ in response to the VF enable clear command CMD. Therefore, the plurality of common functions 730-1 to 730-n associated with the default physical function 720 may be disabled while performing the reset operation.

A virtual function enable clear operation on the above-described common functions 730-1 to 730-n and the associated default physical function 720 may apply to the common functions 730-4 and 730-5 each of which is configured as the virtual function type and the common function 3 730-3 configures as the associated physical function type as shown in the PCIe device 700C of FIG. 12.

FIG. 17 is a flowchart illustrating an operating process of PCIe according to an embodiment of the present disclosure.

The process as shown in FIG. 17 may be performed by, for example, a PCI device including a plurality of common functions, such as the PCIe device 700 as shown in FIG. 7.

Referring to FIG. 17, at step S1701, the PCIe device 700 may receive function type setting information from the host 1000.

For example, the PCIe device 700 may receive the function type setting information by using a technology such as a vendor-defined message, vendor-defined capabilities, new PCIe capability defined by a user, Management Component Transport Protocol (MCTP) over System Manager bus (SMbus), MCTP over PCIe, or the like.

At step S1703, the PCIe device 700 may determine a function type of each of the plurality of common functions as one of a physical function type, a virtual function type and a disable function type based on the function type setting information.

The PCIe device 700 may determine the function type of each of the plurality of common functions by changing values of registers included in the configuration space of each of the plurality of common functions according to the function type setting information.

At step S1705, the PCIe device 700 may control the plurality of common functions to perform operations according to their respective determined function types.

The PCIe device 700 may control one or more first common functions each having a physical function type, among the plurality of common functions, to perform operations based on registers corresponding to the operations included in the configuration space of each of the first common functions.

In addition, the PCIe device 700 may control one or more second common functions each having a virtual function type among the plurality of common functions to perform operations based on registers corresponding to the operations included in the configuration space of a function associated with each of the second common functions.

In addition, the PCIe device 700 may disable registers included in the configuration space of each of one or more third common functions each having a disable function type among the plurality of common functions.

According to the present disclosure, a PCIe device that reduces power consumption and device size by reducing a PCIe-related gate count, and an operating process thereof may be provided.

In addition, according to the present disclosure, a PCIe device efficiently arranging functions configured in various types by using a software process such as a request from a host or by a firmware setting, instead of by hardware modifications, and an operating process thereof may be provided.

While embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible. Thus, it is intended that the present invention cover all such modifications provided they come within the scope of the appended claims and their equivalents. 

What is claimed is:
 1. A peripheral component interconnect express (PCIe) device, comprising: a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types; and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host.
 2. The PCIe device of claim 1, wherein a common function of the plurality of common functions comprises: a configuration space including registers for configuring the common function to perform the operations; and an operation controller controlling the common function to perform the operations according to the determined function type of the common function.
 3. The PCIe device of claim 2, wherein the function type controller determines a function type of the common function from among a plurality of a function types by changing values of the registers included in the configuration space of the common function based on the function type setting information.
 4. The PCIe device of claim 2, wherein the function type controller, based on pointer values indicating capabilities to be enabled among values of the registers, enables capabilities associated with the function type determined for the common function, disables capabilities not associated with the function type determined for the common function, and performs clock gating on registers of the capabilities disabled among the registers.
 5. The PCIe device of claim 2, wherein the function type controller determines the function type of the common function as being one of a physical function (PF) type, a virtual function (VF) type, and a disable function type in which the operations are disabled.
 6. The PCIe device of claim 5, wherein the function type controller disables registers included in the configuration space of the common function when the common function is determined to be the disable function type and performs clock gating on the disabled registers.
 7. The PCIe device of claim 1, wherein the function type setting information includes at least one of a number of common functions to be determined as a physical function type, a number of common functions to be determined as a virtual function type, a number of common functions to be determined as a disable function type, and function type mapping information indicating a mapping relationship between each of the plurality of common functions and the respective function types.
 8. The PCIe device of claim 1, wherein a first common function determined as a physical function type performs the operations based on a base address register (BAR) included in the configuration space of the first common function.
 9. The PCIe device of claim 8, wherein the first common function performs the operations based on registers corresponding to the operations included in the configuration space of the first common function, and performs a reset operation on the first common function in response to a reset request for the first common function provided from the host.
 10. The PCIe device of claim 8, further comprising a default physical function including a base address register included in a configuration space of the default physical function, wherein a second common function determined as the virtual function type has an associated function selected from among the default physical function and the first common function, and performs the operations based on the base address register included in the configuration space of the associated function.
 11. The PCIe device of claim 10, wherein the associated function is a single root I/O virtualization (SR-IOV) capability enabled function, and wherein the second common function is enabled according to a virtual function (VF) enable value included in a SR-IOV capability register of the associated function.
 12. The PCIe device of claim 10, wherein the second common function performs the operations based on registers corresponding to the operations included in the configuration space of the associated function.
 13. The PCIe device of claim 10, wherein the second common function performs a reset operation on the second common function in response to at least one of a reset request for the associated function provided from the host, a reset request for the second common function, and a clear operation of the VF enable value of the associated function.
 14. The PCIe device of claim 1, wherein the operations include at least one of a data processing operation of receiving a command from the host and providing the host with a response to the command, an error handling operation of detecting an error and reporting the error, and a power management operation of managing power of a function.
 15. A method for operating a Peripheral Component Interconnect Express (PCIe) device including a plurality of common functions performing operations associated with a PCIe interface, the method comprising: receiving function type setting information from the host; determining a plurality of function types for the plurality of common functions, respectively, based on the function type setting information, each function type being one of a physical function (PF) type, a virtual function (VF) type, and a disable function type in which the operations are disabled; and controlling the plurality of common functions according to the plurality of function types, respectively, to perform the operations.
 16. The method of claim 15, wherein controlling the plurality of common functions according to the plurality of function types, respectively, comprises changing values of registers included in respective configuration spaces of the plurality of common functions based on the function type setting information.
 17. The method of claim 16, wherein controlling the plurality of common functions comprises controlling a first common functions determined as the physical function type among the plurality of common functions to perform the operations based on registers corresponding to the operations, the registers included in the configuration space of the first common function.
 18. The method of claim 16, wherein controlling the plurality of common functions comprises controlling a second common function determined as the virtual function type among the plurality of common functions to perform the operations based on registers corresponding to the operations that are included in the configuration space of a function associated with the second common function.
 19. The method of claim 16, wherein controlling the plurality of common functions comprises disabling registers included in a configuration space of a third common function determined as the disable function type among the plurality of common functions.
 20. A peripheral component interconnect express (PCIe) device, comprising: a first common function performing operations associated with a Peripheral Component Interconnect Express (PCIe) interface according to a physical function (PF) type; a second common function performing operations associated with the PCIe interface according to the physical function type or a virtual function (VF) type; and a function type controller changing a function type of the second common function into the virtual function type or the physical function type based on function type setting information provided from a host. 